1. Field of Invention
The present invention relates to semiconductor technology, and in particular, to a method for tuning the work function of a metal gate of the PMOS device, which can be used in manufacture of high performance nanoscale complementary Metal-Oxide-Semiconductor Transistor (CMOS) device at 45 nm and beyond.
2. Description of Prior Art
As a feature size of CMOS device reaches the technology node of 45 nm and beyond, it is well known in the art that the structure of high-k (i. e. dielectric constant)/metal gate materials will be used to replace the conventional structure of SiO2/poly-Si for remarkably decreasing the gate tunneling current and the gate resistance, eliminating the depletion effect in polysilicon and the boron penetration problem in PMOSFET (i. e., P-type Metal-Oxide-Semiconductor Transistor), alleviating Fermi level pinning effect, and improving performance of the device. However, there are still some urgent problems in integrating the metal gate with the high-k gate dielectric, such as poor thermal stability, unfavorable interface states, and especially the Fermi level pinning effect which makes the challenging to provide an appropriate low threshold voltage required by nanoscale CMOS devices, in particular, for PMOS devices, because it is more difficult to achieve the high work function required by PMOS devices.